From EP 1 065 706 A2 there are known integrated circuits, semiconductor devices and methods for making the same. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device wafer, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and a deposited oxide.
From WO 94/23444 A2 there is known low temperature wafer bonding using a chemically reacting material between wafers to form a bonded zone to bond two wafers together. Examples include silicon wafers with a silicon-oxidizing bonding liquid which also permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Silicon wafers also may use solid reactants which include deposited layers of metal and polysilicon to form silicide bonded zones. Oxidizers such as nitric acid may be used in the bonding liquid, and a bonding liquid may be used in conjunction with a solid bonding reactant. Dielectric layers on silicon wafers may be used when additional silicon is provided for the bonding reactions. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening and buried resistors.
From U.S. Pat. No. 5,034,343 A there is known a process including bonding a first device wafer to a handle wafer by an intermediate bonding oxide layer and thinning the device wafer to not greater than 7 mils. An epitaxial device layer of under 1 mil may be added. Device formation steps are performed on a first surface of the first device wafer. This is followed by removing the handle wafer to produce a resulting wafer having substantially the thickness of the first device layer. To produce a silicon on insulator (SOI), a third device wafer is bonded to the first surface of the first device wafer by the intermediate oxide layer and the third wafer is thinned to not greater than 40 microns. The first and third device wafers form the resulting SOI wafer.
From U.S. Pat. No. 6,872,640 B1 there are known CMOS devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant through openings in a masking layer and through channel regions of the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) diffusion source within the insulation layer underlying the gate regions of the SOI wafer substantially between the source and drain. Backend high temperature processing steps induce diffusion of the dopants contained in the diffusion source into the p- and n-wells, thereby forming asymmetric retrograde dopant profiles in the channel under the gate. The method can be selectively applied to selected portions of a wafer to tailor device characteristics, such as for memory cells.
From US 2013/0221403 A1, a manufacturing process for a low voltage IGBT of 400 V is known, which has been optimized for low conduction and switching losses while having improved mechanical stability by having a lower thickness in the active area and a higher thickness in the termination area by an increased thickness of the p collector layer. The device is manufactured by providing a p doped CZ wafer and an n-doped FZ wafer, on which an n doped buffer layer has been implanted and annealed. The two wafers are bonded together with a SiO film in between and n-wafer thickness is reduced to 40 μm. Now front sided layers are created and then the wafer is thinned on the back side in the active region, but thickness is maintained in the termination region. Afterwards boron is implanted over the entire back side in the buffer layer in the active region and into the p doped FZ wafer in the termination region. Laser anneal is performed for driving-in the p dopant.
Lowering the production costs is an important goal in the manufacturing of semiconductor devices. One means for lowering the costs in manufacturing of semiconductor devices is to use semiconductor wafers with a larger diameter. Using larger wafers can significantly increase the yield in semiconductor device manufacturing. Semiconductor power devices such as insulated gate bipolar transistors (IGBTs) are meanwhile manufactured on wafers with diameters up to 300 mm.
In fabrication of vertical power devices, such as IGBTs, bi-mode insulated gate transistors (BIGTs), PIN diodes, gate turn off (GTO) thyristors and others, for which the current runs through the device in a direction vertical to the wafer plane, front and back side are to be subjected to production processes. Backside processing includes forming of a buffer layer, an anode layer and/or of a cathode layer by ion implantation and subsequent thermal activation. Since the device thickness does not fit to the SEMI (Semiconductor Equipment and Materials International) standards for the particular wafer sizes handling of thinned wafers must be mastered. Handling of thin large wafers involves the risk of wafer breakage or mechanical damage.
A known manufacturing method for a semiconductor device is explained briefly with reference to FIGS. 1a to 1f. First a low-doped n-type silicon wafer 1 with a front side 2 and a back side 3 as shown in FIG. 1a is subjected to front-end-of-line processing on the front side 2. The term front-end-of-line-processing shall include all semiconductor device manufacturing process steps up to (but not including) the deposition of metallization layers. Exemplarily, it shall include all high temperature process steps with a temperature above 900° C. In case of manufacturing an IGBT front-end-of-line processing results in a topology on the front side 2 of the wafer 1 with inter alia p-type regions 4, oxide layers 5 and poly-silicon gates 6 as shown in FIG. 1b. During all front-end-of-line high temperature treatments an edge termination region (not shown in the figures) is driven into the wafer 1 from its front side 2 up to a depth of 15 μm. Subsequently to the front-end-of-line processing a top metallization layer 7 is formed on the front side. Thereafter the wafer 1 is thinned to obtain a thinned wafer 1′ as shown in FIG. 1c. Thinning of wafer 1 usually includes a combination of mechanical grinding and chemical etching. Next back side processing of the thinned wafer 1′ is performed. In a first step of the back side processing, an n-type buffer layer 8 is formed on the back side 3′ of the thinned wafer 1′ by deep diffusion as shown in FIG. 1d. Thereafter a thin highly doped p-type anode layer 9 is formed on the back side of the thinned wafer by diffusion of a p-type dopant into the thinned wafer 1′ from its backside 3′ as shown in FIG. 1e. The implanted dopants of the n-type buffer layer 8 and of the p-type anode layer 9 have to be activated by a heat treatment. To avoid affecting the processed front side of the wafer laser thermal annealing (LTA) processes are state of the art for activation of the buffer layer 8 and the anode layer 9. A final step of the back side processing is forming of a back side metallization 10 on the anode layer 9 as shown in FIG. 1f. 
In the method described above the thinning process is carried out at a late stage of the manufacturing method after front-end-of-line processing and forming the top metallization layer to minimize the risk of wafer breakage when handling the thinned wafer. A pressure has to be applied in the mechanical grinding process for thinning the wafer and leaves an imprint of any topology or structure formed on the front side surface or in the stack of layers of the wafer. Therefore, uniformity of thinning is deteriorated by the topology formed on the wafer. Further, back side processing requires handling of the thinned wafer and, accordingly, involves the risk of wafer breakage. Also any contact of the front side of the wafer with a wafer support during treatment of the backside results easily in particles on the front side or damaging the front side.
As an alternative approach to further minimize the risk of wafer breakage it can be considered to form the buffer layer before thinning the wafer by deep diffusion. However, the necessary depth of such deep diffusion of the buffer layer increases with increasing thickness of the layer to be removed during the thinning process. Due to the fact that larger wafers have a larger thickness according to the SEMI standards forming of the buffer layer by deep diffusion before thinning of the wafer is not feasible anymore for wafers with a diameter of 200 mm or more.
Manufacturing the device including the buffer layer by epitaxy on a wafer is another possible approach to avoid handling of a thinned wafer and to minimize the risk of wafer breakage. However, epitaxy of semiconductor layers has the disadvantage that it involves higher costs compared to the above described method for manufacturing a semiconductor device.